
`ifndef __SIM__
`include "cbb_ram.v"
`include "cbb_rom.v"
`include "timer.v"
`include "eu.v"
`include "biu.v"
`include "MCL51_top.v"
`include "pxy_bus_mux_2.v"
`include "bus_gpio.v"
`endif 

module top(
    input clk,
    // input rst_n,
    output [0:0] led
);
wire rst_n;
wire [7:0] p0 ;
assign led = p0[0] ;

// MCL51 core 自定义外设扩展总线接口信号 
wire [0:0] pxy_wen ;
wire [7:0] pxy_addr;
wire [7:0] pxy_dout;
wire [7:0] pxy_din ;

// 扩展定时器中断 
wire timer0_int_req ;
wire timer1_int_req ;

//------------------------------------------------  bus 连接线 -------------------------------------------------------
                 
// bus slave 0 wire 
wire [7:0] s0_dat  ; 
wire [7:0] s0_rdt  ; 
wire [7:0] s0_adr ;  
wire s0_wen ;
wire [7:0] s0_addr;    // Slave address prefix
wire [7:0] s0_addr_msk; // Slave address prefix mask
                 
// bus slave 1 wire 
wire [7:0] s1_dat  ; 
wire [7:0] s1_rdt  ; 
wire [7:0] s1_adr ;  
wire s1_wen ;
wire [7:0] s1_addr;    // Slave address prefix
wire [7:0] s1_addr_msk; // Slave address prefix mask   

//------------------------------------------------  bus 地址分配 -------------------------------------------------------
assign {s0_addr , s0_addr_msk } = {8'h00 , 8'hf0} ;
assign {s1_addr , s1_addr_msk } = {8'h10 , 8'hf0} ;  
                            
pxy_bus_mux_2 u_pxy_bus_mux_2  (
    .clk( clk) , 
    .rst_n( rst_n) ,
    .m_dat_i( pxy_dout) ,  
    .m_dat_o( pxy_din)  ,   
    .m_adr_i( pxy_addr) , 
    .m_wen_i( pxy_wen)  ,
                 
    //bus slave 0 output          
    .s0_dat_o( s0_dat)  , 
    .s0_dat_i( s0_rdt)  , 
    .s0_adr_o( s0_adr) , 
    .s0_wen_o( s0_wen)  ,
                 
    //bus slave 0 address configuration
    .s0_addr    ( s0_addr), // Slave address prefix
    .s0_addr_msk( s0_addr_msk), // Slave address prefix mask
                 
    //bus slave 1 output          
    .s1_dat_o( s1_dat)  , 
    .s1_dat_i( s1_rdt)  , 
    .s1_adr_o( s1_adr) , 
    .s1_wen_o( s1_wen)  ,
                 
    //bus slave 1 address configuration
    .s1_addr    ( s1_addr), // Slave address prefix
    .s1_addr_msk( s1_addr_msk)  // Slave address prefix mask
)  ;  


MCL51_top #(
    .MEM_FILE("firmware.hex"),
    .ROM_SIZE(2048),
    .RAM_SIZE(256 + 256) // IRAM + XRAM ; IRAM= 128/256 不能超过256
) mcl51_core
(  
    .CLK(clk),
    .RESET_n(rst_n),

    .p0(p0),
    .int_req({6'h0,timer1_int_req , timer0_int_req}) , //中断请求信号
    .pxy_wen (pxy_wen ),
    .pxy_addr(pxy_addr),
    .pxy_dout(pxy_dout),
    .pxy_din (pxy_din ) 
);



timer     pxy_timer 
(
    .CORE_CLK       (clk),
    .RST_n          (rst_n),
    .ADDRESS        (s0_adr[3:0]),
    .DATA_IN        (s0_dat),
    .DATA_OUT       (s0_rdt),
    .STROBE_WR      (s0_wen),
    .TIMER0_OUT     (timer0_int_req),
    .TIMER1_OUT     (timer1_int_req)  
);


bus_gpio  u_bus_gpio1(
    .clk ( clk ), 
    .rst_n(rst_n) , 

    .m_dat_i( s1_dat)  , 
    .m_dat_o( s1_rdt)  , 
    .m_adr_i( s1_adr) , 
    .m_wen_i( s1_wen)  ,

    .gpio0()
) ;

reg [7:0]reset_latch = 8'h00 ;
assign rst_n = &reset_latch ;
always @(posedge clk ) begin
    reset_latch <= &reset_latch ? reset_latch : reset_latch + 1'b1 ;
end



endmodule 

